Test Reports

Overview

JitterLabs offers two types of Test Reports, discussed in the sections below:

Each Test Report is a fixed price, and is accessed and optionally shared online in the JitterLabs app with a paid subscription. The app allows you to run analyses, export data, and generate custom PDF reports, including Compliance Statements to various standards that you or others create and optionally share.

Test Reports may be created for any device that outputs a clock (or clock-like data) signal having an output frequency from 10 MHz to 26+ GHz. The following are some examples.

Learn how to submit a device for testing

Please contact us anytime for more information.

Standard Test Reports

A Standard Test Report includes a comprehensive set of measurements of general interest to the timing community. Each report includes the following measurements (which are also available for custom testing) at one output frequency, voltage, and temperature. The procedure used to perform each measurement, including post-processing, is fully described in the TEST-1 document.

Lower-frequency Digital Signals

Voltage
output, amplitude, top, base, upper, lower, average, RMS, peak-peak, maximum, minimum, crossing, overshoot, preshoot

Time
duty cycle, frequency, period, pulse width, positive pulse width, negative pulse width

Voltage and Time
transition time, slew rate, frequency versus supply voltage, frequency pushing, frequency versus tuning voltage, tuning sensitivity, VCO modulation bandwidth

Jitter
time-interval error, period jitter, cycle-to-cycle (C2C) jitter, pulse-width jitter, positive pulse-width C2C jitter, negative pulse-width C2C jitter, duty-cycle C2C jitter

Phase/AM Noise
phase noise, phase noise versus tuning voltage, amplitude-modulation noise

Power
power supply induced jitter, signal power versus supply voltage, signal power versus tuning voltage, power-supply current versus supply voltage, power-supply current versus tuning voltage, harmonic power, VCO harmonic power versus tuning voltage

Higher-frequency Digital Signals, and Analog Signals

Voltage and Time
frequency versus supply voltage, frequency pushing, frequency versus tuning voltage, tuning sensitivity, VCO modulation bandwidth

Phase/AM Noise
phase noise, phase noise versus tuning voltage, amplitude-modulation noise

Power
power supply induced jitter, output power versus supply voltage, output power versus tuning voltage, power-supply current versus supply voltage, power-supply current versus tuning voltage, harmonic power, VCO harmonic power versus tuning voltage

See the Notes section below for additional information.

PCIe4 Test Reports

A PCIe4 Test Report is similar to a Standard Test Report, but includes additional measurements required by the PCI Express® BASE v4.0 specification. These measurements provide 100% test coverage for all four PCIe generations (2.5 to 16 GT/s) of common-clock architectures.

Note that SRIS and SRNS architectures are not specified in the PCIe v4.0 BASE specification. However, JitterLabs can also create SRIS and SRNS Test Reports based on your custom requirements (contact us for more information).

All opinions, judgments, recommendations, etc. presented herein are the opinions of JitterLabs and do not necessarily reflect the opinions of the PCI-SIG® association. PCI-SIG®, PCIe® and PCI EXPRESS® are registered trademarks and/or service marks of PCI-SIG.

PCI Express Related Measurements

The following lists all PCIe v4.0 related measurements included in a PCIe4 Test Report. The procedure used to perform each measurement, including post-processing, is fully described in the TEST-2 document.

AC, DC Specifications
rising edge rate, falling edge rate, differential low input voltage, differential high input voltage, absolute crossing-point voltage, variation of crossing-point voltage for rising edges, ring-back voltage margin, time before ring-back voltage is allowed, average clock period accuracy, absolute period, cycle to cycle jitter, absolute min input voltage, absolute max input voltage, duty cycle, rising to falling edge-rate matching, clock source DC impedance, refclk frequency, SSC frequency range, SSC deviation, max SSC df/dt

Jitter
low-frequency jitter mask, GEN-1 jitter (16 filters), GEN-2 jitter (64 filters), GEN-3 jitter (64 filters), GEN-4 jitter (64 filters)

Other Measurements

PCIe4 Test Reports for non-spread spectrum clocks additionally include the following measurements (unrelated to PCI Express) from the Standard Test Report discussed above.

Voltage
output, amplitude, top, base, upper, lower, average, RMS, peak-peak, maximum, minimum, crossing, overshoot, preshoot

Time
duty cycle, frequency, period, pulse width, positive pulse width, negative pulse width

Voltage and Time
transition time, slew rate, frequency versus supply voltage, frequency pushing

Jitter
period jitter, cycle-to-cycle (C2C) jitter, pulse-width jitter, positive pulse-width C2C jitter, negative pulse-width C2C jitter, duty-cycle C2C jitter

Phase/AM Noise
phase noise, amplitude-modulation noise

Power
power supply induced jitter, signal power versus supply voltage, power-supply current versus supply voltage, harmonic power

PCIe4 Test Reports for spread spectrum clocks additionally include the following measurements (unrelated to PCI Express) from the Standard Test Report discussed above.

Voltage
output, amplitude, top, base, upper, lower, average, RMS, peak-peak, maximum, minimum, crossing, overshoot, preshoot

Time
duty cycle, frequency, period, pulse width, positive pulse width, negative pulse width

Voltage and Time
transition time, slew rate, frequency versus supply voltage, frequency pushing

Jitter
period jitter, cycle-to-cycle (C2C) jitter, pulse-width jitter, positive pulse-width C2C jitter, negative pulse-width C2C jitter, duty-cycle C2C jitter

Power
power supply induced jitter

See the Notes section below for additional information.

Compliance Load Boards

JitterLabs provides all required compliance load boards for testing reference clocks to the PCIe v4.0 BASE Specification. Both AC and jitter measurements require passing the clock signal through a differential-transmission line having 15 dB loss at 4 GHz with 2 pF termination.

Customers only need to supply evaluation boards (with the proper termination) for their products. We'll connect the clock outputs from an evaluation board to our compliance load board inputs using short phase-matched cables. The signal flowing through each conductor in the differential trace is measured across a 2 pF terminator using a differential probe.

A second compliance load board (not shown) is used to measure the DC impedance looking into each of the clock's output buffers. The second board is similar to the first, except the output signal connects to an oscilloscope using 3.5 mm connectors instead of probes.

All other measurements, which are unrelated to PCI Express, use the same compliance load board used above for characterizing jitter, except for the following measurements, which connect the evaluation board directly to a signal source analyzer (E5052B) when permitted by the board termination: phase noise, AM noise, signal power versus supply voltage, power-supply current versus supply voltage, and harmonic power.

PFD Compliance Statement

All compliance test results, plus related data and plots, are detailed in an easy to read PDF Compliance Statement that can be downloaded and/or shared using the JitterLabs app.

Click on an example PCIe4 Compliance Statement to view its contents.

Example test report for PCI Express reference clock without spread spectrum clock

Device with SSC Off

(Passing Example)

Example test report for PCI Express reference clock with spread spectrum clock

Device with SSC On

(Failing Example)

Removal of Oscilloscope Random Jitter

The PCI-SIG association requires RMS jitter be measured using a real-time oscilloscope. However, jitter introduced by an oscilloscope can approach or even exceed that from the device being tested, particularly for low-jitter devices.

To remove random jitter introduced by an oscilloscope, and other noise sources in the test environment, we developed a simple method based on empirical modeling. We use this method to accurately extract the intrinsic jitter of a device. Our methodology requires no new hardware, is SSC agnostic, and fulfills all PCI-SIG test requirements. Click the link below to learn more.

Learn how we remove oscilloscope jitter

Notes Applies to all Test Reports